The invention relates to a bit error ratio tester (BERT). More particularly, the invention relates to a low-cost, built-in, at-speed BERT for production testing of high-speed serial links.
The input/output throughput of integrated circuits, for example, programmable logic devices, is currently on the order of gigabits per second and continues to rise. With this high rate of data throughput, an area of concern arises with regard to the bit error ratio. The higher the bit error ratio of a particular device, the more bits that need to be retransmitted, thus decreasing the overall data transfer rate. This clearly makes inefficient the high throughput rates of some of these devices when a high bit error ratio is present.
It therefore becomes important to be able to gauge the bit error ratio of any particular device or type of device. Knowing the bit error ratio of devices allows designers and engineers to choose appropriate devices that are required to exhibit a particular (e.g., minimum) data transfer rate for a particular design or application.
Bit error ratios are typically ascertained through the use of a bit error ratio tester (BERT). A BERT includes a pattern generator and an error detector/analyzer that are used to construct a bathtub curve (also known as a BERT scan). The bathtub curve is a plot of the bit error ratio versus sampling time that is generated by stepping a sampling point across a data eye. The conventional bathtub curve test requires a stand-alone BERT which is expensive and unsuitable for low-cost production testing of high-speed serial links.
It would therefore be desirable to provide a low-cost, built-in, at-speed BERT for production testing of high-speed serial links.